Resistive Switching

With its comprehensive coverage, this reference introduces readers to the wide topic of resistance switching, providing the knowledge, tools, and methods needed to understand, characterize and apply resistive switching memories.

Starting with those materials that display resistive switching behavior, the book explains the basics of resistive switching as well as switching mechanisms and models. An in-depth discussion of memory reliability is followed by chapters on memory cell structures and architectures, while a section on logic gates rounds off the text.

An invaluable self-contained book for materials scientists, electrical engineers and physicists dealing with memory research and development.

INTRODUCTION
 
TRANSITION METAL OXIDES
Atomic Structures of Selected Binary, Ternary Oxides
Deposition Techniques
Thermodynamics of Oxidation, Ellingham Diagram
Electronic Structure and Conduction
Correlated Electrons
Ionic Conduction
 
RESISTIVE SWITCHING
Device Structure
Unipolar Switching: Forming, Set/Reset Operations
Bipolar Switching: Forming, Set/Reset Operations
Coexistence of Unipolar/Bipolar Switching
Filamentary Switching and Atomic Force Microscopy Analysis
Interface Switching
Threshold and Memory Switching
Time Dependence of Set/Reset
Resistance Dependence of Set/Reset
 
SWITCHING MECHANISMS AND MODELS
Unipolar Switching: Set/Reset Mechanisms and Models
Bipolar Switching: Set/Reset Mechanisms and Models
Modeling of Resistance Dependence (Filament Size and Gap)
Modeling of Time Dependence
Modeling of Set Current Dependence
Overshoot and Parasitic Effects
Material Dependence and Universal Switching
 
MEMORY RELIABILITY
Read Disturb and The Time-Voltage Dilemma
Data Retention
1/f and Random Telegraph Signal Noise
Switching Variability and Set/Reset Algorithms
Reset Current Reduction
Set/Reset Instability
Cycling Endurance
 
MEMORY CELL STRUCTURES
MIM Structures
Bilayered Structures
Lighting-Rod Structures
Contact RRAM
Complementary Resistance Switch (CRS)
Multilevel Cells
Alternative Materials: OxRRAM, PoRRAM, CBRAM
Bottom-Up Approaches: Nanotubes, Nanowires and Self-Assembly
 
MEMORY ARCHITECTURES
Crossbar Array
Diode Selectors
Transistor Selectors
1T1R Architectures
CMOL
Scaling Issues (Series Resistance, Programming Cross Talk, 3D Stacking Issues)
 
LOGIC GATES
The Memristor
Crossbar Latch
Data Restoration
IMP Function
STDP in Memristor Gates
 
CONCLUSIONS

• Edited by Daniele Ielmini
• Edited by Rainer Waser